Espressif Systems /ESP32-S3 /SENSITIVE /CORE_1_PIF_PMS_CONSTRAIN_5

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Interpret as CORE_1_PIF_PMS_CONSTRAIN_5

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1

Description

Core1 access peripherals permission configuration register 5.

Fields

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART

Core1 access uart permission in world1.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1

Core1 access g0spi_1 permission in world1.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0

Core1 access g0spi_0 permission in world1.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO

Core1 access gpio permission in world1.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2

Core1 access fe2 permission in world1.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE

Core1 access fe permission in world1.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC

Core1 access rtc permission in world1.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX

Core1 access io_mux permission in world1.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF

Core1 access hinf permission in world1.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC

Core1 access misc permission in world1.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C

Core1 access i2c permission in world1.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0

Core1 access i2s0 permission in world1.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1

Core1 access uart1 permission in world1.

Links

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